-- Vhdl instantiation template created from schematic C:\xilinks\Pokus2\D147D.sch - Wed Apr 07 08:50:09 2010
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module.
-- 2) To use this template to instantiate this component, cut-and-paste and then edit.
--

   COMPONENT D147D
   PORT( A	:	IN	STD_LOGIC; 
          B	:	IN	STD_LOGIC; 
          C	:	IN	STD_LOGIC; 
          D	:	IN	STD_LOGIC; 
          LT	:	IN	STD_LOGIC; 
          RBI	:	IN	STD_LOGIC; 
          Qa	:	OUT	STD_LOGIC; 
          Qb	:	OUT	STD_LOGIC; 
          Qc	:	OUT	STD_LOGIC; 
          Qd	:	OUT	STD_LOGIC; 
          Qe	:	OUT	STD_LOGIC; 
          Qf	:	OUT	STD_LOGIC; 
          Qg	:	OUT	STD_LOGIC);
   END COMPONENT;

   UUT: D147D PORT MAP(
		A => , 
		B => , 
		C => , 
		D => , 
		LT => , 
		RBI => , 
		Qa => , 
		Qb => , 
		Qc => , 
		Qd => , 
		Qe => , 
		Qf => , 
		Qg => 
   );
